An FPGA Implementation of a Chaotic Encryption Algorithm
Autore
Lorenzo Cappelletti - Università degli Studi di Padova - [1999-00]
Documenti
Abstract
Visual sight is an important and easy sense of communication. Recently, since computer speed, media storage and network bandwidth
have seen great improvements of their performances, imaging has gained even more importance along with security, privacy and intellectual property defense.
In order for a complex imaging system to cope with these concerns, a cryptography scheme able to manage the vast amounts of data involved in image processing is required. So far, many image encryption algorithms have been restricted to the software realm, primarily due to its ease of use, ease of update, portability and flexibility. But
when throughput and secret key storage security become a major issue, hardware implementations are by nature more physically secure and potentially faster.
This work aims to investigate hardware feasibility and performance of an encryption technique proposed by J.Scharinger, and based on the highly unstable non-linear dynamics of chaotic Kolmogorov flows. The algorithm is particularly attractive since only additions,
subtractions and bit-shifts are required and no time-consuming operations like multiplications or exponentiation.
In this context, re-programmable devices such as FPGAs are highly attractive options since they provide hardware agility, parameterization and developing cost efficiency. The chip chosen for the implementation is a Xilinx's Virtex XCV400BG432-6, whose embedded RAM allows manipulation of small images directly in situ.
have seen great improvements of their performances, imaging has gained even more importance along with security, privacy and intellectual property defense.
In order for a complex imaging system to cope with these concerns, a cryptography scheme able to manage the vast amounts of data involved in image processing is required. So far, many image encryption algorithms have been restricted to the software realm, primarily due to its ease of use, ease of update, portability and flexibility. But
when throughput and secret key storage security become a major issue, hardware implementations are by nature more physically secure and potentially faster.
This work aims to investigate hardware feasibility and performance of an encryption technique proposed by J.Scharinger, and based on the highly unstable non-linear dynamics of chaotic Kolmogorov flows. The algorithm is particularly attractive since only additions,
subtractions and bit-shifts are required and no time-consuming operations like multiplications or exponentiation.
In this context, re-programmable devices such as FPGAs are highly attractive options since they provide hardware agility, parameterization and developing cost efficiency. The chip chosen for the implementation is a Xilinx's Virtex XCV400BG432-6, whose embedded RAM allows manipulation of small images directly in situ.
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