High Throughput Turbo Decoder for HSDPA
Autore
Teo Cupaiuolo - Technical Univerisity of Turin, Swiss Federal Institut of Technology - [2006]
Documenti
Abstract
Turbo codes are of great interest since they are able to provide better performance than other known coding techniques. Moreover they are included in the UMTS standard.
In this thesis the design of a 3GPP compliant turbo decoder for HSDPA application is proposed. Various architectural trade-offs are analyzed and appropriate choices are made in order to achieve the high data rates required by the standard. In the end, the recursion level parallelized SW SMAP architecture with alpha approach has been implemented, together with a hardware interleaver able to generate the address required for the interleaving on-the-fly. The turbo decoder is also able to handle all the block lengths specified by 3GPP.
The developed architecture has been synthesized and the clock frequency is 100 MHz in UMC 0.13 CMOS process. The turbo decoder reaches a maximum data rate of 8.9 Mbits/s for a block length of 5114 bits at 100 MHz and with six iterations.
In this thesis the design of a 3GPP compliant turbo decoder for HSDPA application is proposed. Various architectural trade-offs are analyzed and appropriate choices are made in order to achieve the high data rates required by the standard. In the end, the recursion level parallelized SW SMAP architecture with alpha approach has been implemented, together with a hardware interleaver able to generate the address required for the interleaving on-the-fly. The turbo decoder is also able to handle all the block lengths specified by 3GPP.
The developed architecture has been synthesized and the clock frequency is 100 MHz in UMC 0.13 CMOS process. The turbo decoder reaches a maximum data rate of 8.9 Mbits/s for a block length of 5114 bits at 100 MHz and with six iterations.
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