Contatta l'autore

Sadiq Ullah Khan Yousafzai - University of Engg. & Technology Taxila Pakistan - [2005]

Preview

Indice

Bibliografia

Tesi completa: 79 pagine

This thesis describes the VLSI design & implementation of Integer Transform (IT) & quantization module for H.264/AVC. The design aims to provide significant complexity saving as well as adaptively controlling the computational complexity. Integer transform architecture is proposed for taking 4x4 pixels blocks of residual video data as an input. The integer transform is designed to remove the spatial redundancy in the video input which results in compression. The 4x4 integer transform is further reduced to two 2x2 sub-transforms. The two 2x2 matrix operations are performed in parallel thus satisfying the pipeline architecture which makes it more efficient. The multiplications in the transform operation are performed by simple left-shift operations while the division operation in the quantization process is achieved through right-shift operation. According to this design, 2-D transform is implemented by using duplicated l-D transform. It is shown that this architecture can flexibly control the computational complexity of each function with negligible loss of video quality. Using Xilinx® Vertex-2 FPGA technology, the logic gate count is only 4524, critical path delay is 8.104ns , output delay is only 22 clock cycles, & the maximum operational frequency is 127MHz.

Key words: , ,

• Ingegneria Informatica
• Ingegneria Telecomunicazioni