Cache-Simulator of a MultiProcessor Architecture for AXE CP
Autore
Mirco Porcari - Politecnico di Milano - [1998-99]
Documenti
Abstract
Due to the increased capacity need for the telecommunication servers, an idea to be investigated is represented by the use of symmetric multiprocessor architectures instead of the currently employed uniprocessors. One important aspect affecting the efficiency of such systems is the structure and behaviour of the caches.
This master thesis presents a cache simulator for symmetric multiprocessor systems (SMP), able to estimate the performances of a wide number of different memory configurations. The simulator reads trace files recorded from a multiprocessor prototype running traffic for a telecommunication environment. The user chooses the parameters characterising configuration and policies of the cache systems. However, the program is designed to be more general and, thanks to the object-oriented methodology adopted, it is flexible and easily extendible.
The most important bottleneck for this kind of systems is the bus bandwidth: from our results we can determine what are the factors that mostly affect the performances and individuate possible solutions.
This master thesis presents a cache simulator for symmetric multiprocessor systems (SMP), able to estimate the performances of a wide number of different memory configurations. The simulator reads trace files recorded from a multiprocessor prototype running traffic for a telecommunication environment. The user chooses the parameters characterising configuration and policies of the cache systems. However, the program is designed to be more general and, thanks to the object-oriented methodology adopted, it is flexible and easily extendible.
The most important bottleneck for this kind of systems is the bus bandwidth: from our results we can determine what are the factors that mostly affect the performances and individuate possible solutions.
Questa tesi è correlata alle categorie
segnala questa pagina ::.